1. Field of the Invention
This invention relates in general to a display device for showing video information whose number of scanning lines changes over elapsed time per each field, and relates in particular to a display device which is ideal for preventing vertical jitter from occurring during the display of video information having changes in the number of scanning line that occur at random. This invention is suited for display, for instance, of digital broadcasts, or joint display of both digital broadcasts and analog broadcasts.
2. Description of the Related Art
Digital technology has been making steady progress in the area of broadcasting in recent years. In order for display equipment such as, for instance, television receivers to keep pace with this progress, the display equipment must be able to display digital broadcast signals as well as analog broadcast signals and VTR playback signals. Circuit systems are therefore being designed to make receivers compatible with digital broadcasts. A decoded digital broadcast signal is therefore written temporarily into a field memory and then utilized in a readout system. Analog signals of the currently used NTSC method are subjected to analog/digital (A/D) conversion and then input to a digital signal processing circuit and written along with the digital broadcast signal into a field memory.
The writing and reading of video information into the field memory is performed by utilizing the read block and vertical and horizontal synchronizing signals. However, when the digital broadcast signal is, for instance, an MPEG2 type signal and has been compressed, no synchronizing signal is sent from the transmitter. Accordingly, a synchronizing signal must be generated and a read signal formed by the receiver in order to read out the information from the field memory. However, a difference in frequency sometimes occurs between the write signal for writing into the field memory, and the read signal for readout from the field memory. This difference in frequency results in reversed timing or an opposite phenomenon called xe2x80x9cskipxe2x80x9d occurring between the memory writing and readout operations.
When this memory skip occurs, the current field image on one frame of the screen and the image from one previous field are mixed together, thus requiring some contrivance to prevent memory skip from occurring. The changes particularly in the vertical frequency are particularly large in cases such as the custom playback of VTR signals. One method to prevent memory skip from occurring at such times is by changing the number of scanning lines per field. One example of this is television receivers in Europe capable of receiving broadcast teletext or subscript transmissions. These receivers are set to have alternate scanning lines of 312 lines by 313 lines per field (PAL etc.) or 262 lines by 263 lines (NTSC) with non-interlaced scanning used for display of the teletext broadcast screen.
However, a feedback circuit for uniform vertical amplitude is provided in the vertical deflection circuit of the CRT display. Consequently, a vertical jitter at 60 Hz occurs when attempting to display video information in which the alternate scanning lines are 312 lines by 313 lines (or 262 by 263 lines) per field on the CRT display. A technology that has been proposed to reduce this vertical jitter is disclosed in Japanese Examined Utility Model Publication No. 7-44130. This method isolates the circuit for aligning vertical amplitude and the feedback circuit, and utilizes a differentiator circuit consisting of a resistor and capacitor to cut the DC components and apply feedback signals to the vertical amplifier amplitude control terminal.
However, in video information formed for a system designed for joint use of conventional analog broadcasts and expanding systems utilizing MPEG2 for handling digital broadcasts, the number of scanning lines will not always mutually increase and decrease per field. In such cases, the increase or decrease in the number of scanning lines per field will be a factor appearing randomly in the synchronizing signal status of the input signal. Consequently, vertical jitter will still be difficult to suppress, even if the technology disclosed in the above patent is adopted in the above system, since the system permits creation of video information in which changes in the number of scanning lines per field appear at random.
This invention, which takes the above problems into account, has the objective of providing a display capable of satisfactory suppression of vertical jitter, even when displaying video information in which changes in the number of scanning lines per field appear at random.
In order to achieve the above mentioned objectives, this invention is characterized in being comprised of a receiving means to receive digital broadcast, a decoding means to decode the digital broadcast signal from the receiving means and then output video information containing at least a first and a second field with a mutually different number of scanning lines, a display means to display images utilizing the video information output from the decoding means, and a display control means for setting the same start position for the first and the second fields on the screen of the display means.
The display unit of this invention is comprised of a memory for storing the video information output from the decoding means, a clock generator to generate a read clock for readout of video information stored in the memory, and a D/A (digital/analog) converter to perform digital to analog conversion of the video information read out from the memory and supply the converted information to the display means.
The display control means may also be comprised of a vertical ramp waveform generator circuit to generate a vertical ramp waveform for performing vertical deflection, and a clamp circuit to maintain a uniform voltage for the first field and the second field that corresponds to the vertical retrace period of the vertical ramp waveform formed in the vertical ramp waveform generator circuit.
This vertical ramp waveform generator circuit operates in synchronization with a vertical synchronizing signal and may contain a switch to charge the capacitor with electrical current from the power supply during the vertical scanning period and to discharge the capacitor during the vertical retrace period.
The clamp circuit is synchronized with the vertical synchronizing signal and may include a switch to link the fixed DC voltage to the vertical ramp waveform.
The vertical ramp waveform generator circuit is further comprised of a counter to count the read clock generated by the clock generator, and a D/A converter to perform digital to analog conversion of the output signal from the counter and output a vertical ramp waveform. The clamp circuit may include a reset circuit to reset the count from the counter according to the vertical synchronizing signal.
The display control means may be comprised of a vertical ramp waveform generator circuit, a comparator to compare a reference voltage corresponding to a reference number of scanning lines per one field versus a voltage corresponding to a number of scanning lines for the first field and the second field read out from the memory, and output a control signal according to the comparison results, and a variable voltage power supply for controlling the direct current component of the vertical ramp waveform for performing vertical deflection according to the control signal output from the comparator.
The display control means may be comprised of a vertical ramp waveform generator means to generate a vertical ramp waveform for performing vertical deflection, and an amplifier control means to control feedback of the amplitude of the vertical ramp waveform generated in the vertical ramp waveform generator means.
The amplitude control means includes a rectifier to rectify the vertical ramp waveform, and if the rectifier time constant is set at 80-120 ms, then there is no follow-up (slaving) to changes in the field frequency between a plurality of fields.
The amplitude control means may also be provided with a rectifier to rectify the vertical ramp waveform, and a time constant adjustment circuit to adjust the time constant of the rectifier according to the status of the display unit.
This time constant adjustment circuit may adjust the time constant when power to the display device is turned on in order to make the time constant smaller than in normal operation. In such a case, the time constant may be set at 10 ms or less at the time when the power to the display device is turned on, and set at 400-600 ms during normal operation.